Sigmoid Linear Unit (Swish)
— unknown status| Operation | SiLU (bpd_silu) |
|---|---|
| Formula | f(x) = x · sigmoid(x) |
| Category | Transcendental (exp) |
This is the backend-neutral op_expr fact that specifies the operation. The same term is lowered to LLVM IR, CUDA C, MLIR, and every other backend — one specification, many targets.
op_expr(bpd_silu,
div(var,
add(const(1.0), call(exp, neg(var))))).
| Backend | LLVM NVPTX (llvm_nvptx) |
|---|---|
| Target | nvptx |
| Description | LLVM IR targeting NVIDIA PTX (GPU). Compiled with llc for nvptx64, loaded via CUDA driver API. |
This is the actual LLVM IR (NVPTX) emitted by our Prolog/Logtalk toolchain for this operation. Every instruction was generated from a declarative op_expr specification — no hand-written assembly.
; GENERATED from op_expr(bpd_silu) via lower_llvm — backend 4 (shared AST).
declare float @llvm.exp.f32(float)
define void @silu(float* noalias %src, float* noalias %dst, i64 %n) {
entry:
br label %loop
loop:
%i = phi i64 [0, %entry], [%inext, %body]
%cond = icmp slt i64 %i, %n
br i1 %cond, label %body, label %done
body:
%sp = getelementptr float, float* %src, i64 %i
%v = load float, float* %sp, align 4
%l0 = fadd float 0.0, 1.0
%l1 = fneg float %v
%l2 = call float @llvm.exp.f32(float %l1)
%l3 = fadd float %l0, %l2
%l4 = fdiv float %v, %l3
%dp = getelementptr float, float* %dst, i64 %i
store float %l4, float* %dp, align 4
%inext = add i64 %i, 1
br label %loop
done:
ret void
}
| Tier | SILVER — 0 ULP, robustness testing pending |
|---|---|
| ULP Divergence | 0 |
| Source Commit | b03bc23f7 |
| Deployment | deployed |
| Measured | 2026-09-25 |
| Hardware | NVIDIA Tesla P4 (enclave GPU) |
| Gate | Output compared to PyTorch reference on identical input tensor. 0 ULP = every floating-point bit matches. |
