Scaled Exponential Linear Unit
— unknown status| Operation | SELU (bpd_selu) |
|---|---|
| Formula | f(x) = λ · (x if x > 0, else α(exp(x) - 1)), λ≈1.0507, α≈1.6733 |
| Category | Transcendental (exp) |
This is the backend-neutral op_expr fact that specifies the operation. The same term is lowered to LLVM IR, CUDA C, MLIR, and every other backend — one specification, many targets.
op_expr(bpd_selu,
mul(const(1.0507009873554805),
sel(le(var, const(0.0)),
mul(const(1.6732632423543772),
sub(call(exp, var), const(1.0))),
var))).
| Backend | LLVM NVPTX (llvm_nvptx) |
|---|---|
| Target | nvptx |
| Description | LLVM IR targeting NVIDIA PTX (GPU). Compiled with llc for nvptx64, loaded via CUDA driver API. |
This is the actual LLVM IR (NVPTX) emitted by our Prolog/Logtalk toolchain for this operation. Every instruction was generated from a declarative op_expr specification — no hand-written assembly.
; BPD selu: lambda * (x if x>0, alpha * expm1(x) if x<=0)
; Precomputed: lambda*alpha = 1.7580993 (0x3FFC212CC0000000)
define void @bpd_selu(i32 %n, float* %out, float* %in) {
entry:
%cmp = icmp sgt i32 %n, 0
br i1 %cmp, label %loop, label %exit
loop:
%i = phi i32 [ 0, %entry ], [ %next, %store ]
%idx = sext i32 %i to i64
%inptr = getelementptr float, float* %in, i64 %idx
%x = load float, float* %inptr, align 4
%positive = fcmp ogt float %x, 0.0
br i1 %positive, label %pos, label %neg
pos:
%pos_result = fmul float %x, 0x3FF0CFABE0000000
br label %store
neg:
%expm1_val = call float @expm1f(float %x)
%neg_result = fmul float %expm1_val, 0x3FFC212CC0000000
br label %store
store:
%result = phi float [ %pos_result, %pos ], [ %neg_result, %neg ]
%outptr = getelementptr float, float* %out, i64 %idx
store float %result, float* %outptr, align 4
%next = add i32 %i, 1
%done = icmp sge i32 %next, %n
br i1 %done, label %exit, label %loop
exit:
ret void
}
declare float @expm1f(float)
| Tier | SILVER — 0 ULP, robustness testing pending |
|---|---|
| ULP Divergence | 0 |
| Source Commit | b03bc23f7 |
| Deployment | deployed |
| Measured | 2026-09-25 |
| Hardware | NVIDIA Tesla P4 (enclave GPU) |
| Gate | Output compared to PyTorch reference on identical input tensor. 0 ULP = every floating-point bit matches. |
